This Package contains the HSPICE models of the 2Gbit DDR2 SDRAM component in
nominal, slow and fast PVT cases for x4/x8/x16 I/O configuration
README.txt - This File
/nom/main.inc - Input file at nominal condition
/nom/ddr2_2gb_x?.inc - Encrypted netlist of circuits at nominal condition
/slow/main.inc - Input file at slow-slow corner
/slow/ddr2_2gb_x?.inc - Encrypted netlist of circuits at slow-slow corner
/fast/main.inc - Input file at fast-fast corner
/fast/ddr2_2gb_x?.inc - Encrypted netlist of circuits at fast-fast corner
Usage
=====
Please simulate for each models the main.inc file.
For each model type, 3 directories are available, corresponding to a specific corner :
- nom/ : TYPICAL, vddq=vext=1.8V, 25 deg C,
- slow/ : SLOW-SLOW, vddq=vext=1.7V, 95 deg C,
- fast/ : FAST-FAST, vddq=vext=1.9V, 0 deg C.
For changing these corners, please edit the respective main.inc files.
********OCD parameter and truth table description***********
******************************************************************************************************
.param emr1_a1=0/1 Normal/Reduced OCD strength EMRS(0 = full strength, 1=reduced strength)
emr1_a1 | Output strenght
-------------------------------------------------------------
0 | full driver strengh(100%)
1 | weak driver strength(60%)
OCDs Truth Table:
=================
Pin dq_en | Pin dq_in | param emr1_a1 | Output
dqs_en | dqs_in | |
rdqs_en | rdqs_in | |
------------------------------------------------------------------------
low | x | x | Hi-Z
high | low | 0 | 0 full driver strength
high | low | 1 | 0 weak driver strength
high | high | 0 | 1 full driver strength
high | high | 1 | 1 weak driver strength
Note : low = vssq; high = vddq
On-Die Termination Truth Table:
===============================
.param emr1_a2=0/1 75 Ohm ODT EMRS(0=off, 1=on)
.param emr1_a6=0/1 150 Ohm ODT EMRS(0=off, 1=on)
odt_en | parameter emr1_a6 | parameter emr1_a2 | Termination Value |
---------------------------------------------------------------------------------------
low | 0 | 0 | no On-die Termination |
high | 0 | 0 | no On-die Termination |
high | 1 | 0 | 150 Ohm On-die Termination |
high | 0 | 1 | 75 Ohm On-die Termination |
high | 1 | 1 | 50 Ohm On-die Termination |
Note : low = vssq; high = vddq
****************************************************************************************
***********************signal description in all models*********************************
****************************************************************************************
***********************************************
Input Signals configuration Description Voltage levels
------------- ------------ ------------- --------------
vddq x4/x8/x16 OCD power high potential, nominal 1.8V SSTL18
vssq x4/x8/x16 OCD power low potential (GROUND reference) SSTL18
dq_en x4/x8/x16 output enable of DQ pins SSTL18
dqs_en x4/x8/x16 output enable of DQS pins SSTL18
rdqs_en x4/x8/x16 output enable of RDQS pins SSTL18
odt_en x4/x8/x16 ODT enable SSTL18
dqs_t_in x4/x8/x16 pin to stimulate the 'dqs' (true signal) OCD data strobe SSTL18
dqs_c_in x4/x8/x16 pin to stimulate the 'bdqs' (complement signal) OCD data strobe SSTL18
dm_rdqs_t_in x4/x8/x16 pin to stimulate the 'rdqs' (true signal) OCD data strobe SSTL18
nu_rdqs_c_in x4/x8/x16 pin to stimulate the 'brdqs' (complement signal) OCD data strobe SSTL18
dq_in<xx> x4/x8/x16 pin to stimulate the I/O data OCDs SSTL18
dqs_t x4/x8/x16 'dqs_t' OCD output / 'dqs_t' receiver input, at package ball SSTL18
dqs_c x4/x8/x16 'dqs_c' OCD output / 'dqs_c' receiver input, at package ball SSTL18
dm_rdqs_t x4/x8/x16 'rdqs_t' OCD output / 'dm' receiver input, at package ball SSTL18
nu_rdqs_c x4/x8/x16 'rdqs_c' OCD output , at package ball SSTL18
dq<xx> x4/x8/x16 'dq' data OCD outputs /'dq' data receiver inputs, at package ball SSTL18
vref x4/x8/x16 reference voltage for DQ receiver (vext!/2.0), at package ball SSTL18
odt x4/x8/x16 ODT enable pin, at package ball SSTL18
cke x4/x8/x16 cklock enable pin, at package ball SSTL18
ck_t x4/x8/x16 clock input - true signal -, at package ball SSTL18
ck_c x4/x8/x16 clock bar input - complement signal -, at package ball SSTL18
we_n x4/x8/x16 write enable (bar), at package ball SSTL18
cas_n x4/x8/x16 Column Address Strobe (bar), at package ball SSTL18
ras_n x4/x8/x16 Row Address Strobe (bar), at package ball SSTL18
cs_n x4/x8/x16 Chip Select (bar), at package ball SSTL18
a<xx> x4/x8/x16 Address signals, at package ball SSTL18
ba<xx> x4/x8/x16 Bank Address bus, at package ball SSTL18
pad_vref x4/x8/x16 reference voltage for DQ receiver (vext!/2.0), at chip pad
pad_odt x4/x8/x16 ODT enable pin, at chip pad
pad_cke x4/x8/x16 cklock enable pin, at chip pad
pad_ck_t x4/x8/x16 clock input - true signal -, at chip pad
pad_ck_c x4/x8/x16 clock bar input - complement signal -, at chip pad
pad_we_n x4/x8/x16 write enable (bar), at chip pad
pad_cas_n x4/x8/x16 Column Address Strobe (bar), at chip pad
pad_ras_n x4/x8/x16 Row Address Strobe (bar), at chip pad
pad_cs_n x4/x8/x16 Chip Select (bar), at chip pad
pad_a<xx> x4/x8/x16 Address signals, at chip pad
pad_ba<xx> x4/x8/x16 Bank Address bus, at chip pad
pad_dqs_t x4/x8/x16 'dqs_t' OCD output / 'dqs_t' receiver input, at chip pad
pad_dqs_c x4/x8/x16 'dqs_c' OCD output / 'dqs_c' receiver input, at chip pad
pad_dm_rdqs_t x4/x8/x16 'rdqs_t' OCD output / 'dm' receiver input, at chip pad
pad_nu_rdqs_c x4/x8/x16 'rdqs_c' OCD output , at chip pad
pad_dq<xx> x4/x8/x16 'dq' data OCD outputs / 'dq' data receiver inputs, at chip pad
Remark
======
Model created with HSpice version:
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HSPICE Y-2008.03 Copyright (C) 2008 Synopsys |